1. Field of the Invention
The present invention relates to techniques for improving computer system performance. More specifically, the present invention relates to a method and an apparatus for avoiding register read-after-write (RAW) hazards when returning from speculative execution.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.
Efficient caching schemes can help reduce the number of memory accesses that are performed. However, when a memory reference, such as a load operation generates a cache miss, the subsequent access to level-two (L2) cache or memory can require dozens or hundreds of clock cycles to complete, during which time the processor is typically idle, performing no useful work.
A number of techniques are presently used (or have been proposed) to hide this cache-miss latency. Some processors support out-of-order execution, in which instructions are kept in an issue queue, and are issued “out-of-order” when operands become available. Unfortunately, existing out-of-order designs have a hardware complexity that grows quadratically with the size of the issue queue. Practically speaking, this constraint limits the number of entries in the issue queue to one or two hundred, which is not sufficient to hide memory latencies as processors continue to get faster. Moreover, constraints on the number of physical registers which are available for register renaming purposes during out-of-order execution also limits the effective size of the issue queue.
Some processor designers have proposed entering a “scout mode” during processor stall conditions. In scout mode, instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the processor. For example, see U.S. patent application Ser. No. 10/741,944, filed 19 Dec. 2003, entitled, “Generating Prefetches by Speculatively Executing Code through Hardware Scout Threading,” by inventors Shailender Chaudhry and Marc Tremblay. This solution to the latency problem eliminates the complexity of the issue queue and the rename unit, and also achieves memory-level parallelism. However, it suffers from the disadvantage of having to re-compute results of computational operations that were performed in scout mode.
To avoid performing these re-computations, processor designers have proposed entering an “execute-ahead” mode, wherein instructions that cannot be executed because of unresolved data dependencies are deferred, and wherein other non-deferred instructions are executed in program order. When an unresolved data dependency is ultimately resolved during execute-ahead mode, the system executes deferred instructions in a deferred-execution mode, wherein deferred instructions that able to be executed are executed in program order, and wherein other deferred instructions that still cannot be executed because of unresolved data dependencies are deferred again. For example, see U.S. patent application Ser. No. 10/686,061, filed 14 Oct. 2003, entitled, “Selectively Deferring the Execution of Instructions with Unresolved Data Dependencies as They Are Issued in Program Order,” by inventors Shailender Chaudhry and Marc Tremblay.
Scout mode, execute-ahead and deferred mode are all forms of “speculative execution,” wherein the processor first performs a checkpointing operation to preserve the architectural state of the processor, and then executes subsequent instructions speculatively. In scout mode, instructions are executed to prefetch future loads but the results of the instructions are not used for other purposes. Hence, the processor must eventually return to the launch-point instruction (which caused the processor to leave normal-execution mode) to resume normal non-speculative execution.
In contrast, during execute-ahead mode and deferred mode, it is possible for all of the deferred instructions to complete successfully, in which case results of the instructions completed during execute-ahead mode and deferred mode are committed to the architectural state of the processor. However, if a non-data dependent stall condition is encountered during execute-ahead mode or deferred mode, the processor may enter scout mode, in which case the processor will eventually use the checkpoint to return to the launch point instruction.
If the processor quickly returns from speculative execution, inter-instruction data dependencies can potentially cause a register read-after-write (RAW) hazard to arise. Some conventional in-order processors, which do not support speculative execution, maintain a “short-latency scoreboard,” which keeps track of register dependencies between short-latency instructions. This enables such processors to delay issuance of instructions that depend upon uncompleted short-latency instructions, thereby preventing register RAW hazards from occurring during normal execution.
However, if a processor returns quickly from speculative execution, it is possible for a short-latency instruction, which was issued prior to entering speculative-execution mode, to not have produced a forwardable result. In this case, a RAW hazard can potentially arise unless the issuance of subsequent dependent instructions can be delayed until the short-latency instruction completes.
Hence, what is needed is a method and an apparatus for avoiding register RAW hazards upon returning from speculative execution.